Electrical interconnections are required for electrically connecting an integrated circuit to the electrical circuit on the supporting substrate. Typically, the integrated circuit has small solder balls or "bumps" attached to those regions where electrical contact will be made. The integrated circuit is then positioned such that the bumps contact the electrical circuit on the supporting substrate in the appropriate regions.
In addition to the conventional thick and thin film technologies wherein the electrical circuit is printed or deposited onto the surface of a supporting substrate so as to form the patterned circuitry, many methods are known for forming the electrical interconnections between an integrated circuit and the electrical circuit on a supporting substrate. Tape automated bonding (TAB) is one commonly known method for forming these such electrical interconnections. A TAB tape is provided which comprises a plurality of individual long, slender inner leads attached to, and extending out from, generally wider, larger outer leads. There may be many of these inner/outer lead configurations on a single TAB tape.
An individual inner lead on the TAB tape is bonded to the integrated circuit at a bonding pad, so as to form an inner lead bond. There are generally many of these inner lead bonds on a single integrated circuit. The inner lead bonds are typically formed by first depositing a gold bump, or other suitable material, on the integrated circuit itself at the appropriate electrical connection points. The integrated circuit and TAB tape inner leads, which are generally copper, are then aligned and simultaneously thermocompression gang bonded.
After bonding between the integrated circuit and inner leads is complete, the integrated circuit is excised from the TAB tape at a point beyond the outer lead, so that the outer lead remains attached to the bonded inner lead and integrated circuit. The integrated circuit assembly is subsequently mounted on a substrate, if this has not already been done, and the outer leads are appropriately bonded to the substrate.
In an alternative bonding method, a flexible circuit (FLEX) is used to form the electrical interconnections between the integrated circuit and the substrate, the substrate being an integral part of the flexible circuit itself. The FLEX circuit consists of a patterned arrangement of conductors on a flexible insulating base substrate with or without cover layers. The FLEX circuit may be single or double sided, multi-layered, or rigidized, in addition to other possible arrangements. The FLEX circuit may be formed by several methods, such as by laminating copper foil to any of several base substrate materials, or alternatively pattern plating copper directly onto the substrate.
The FLEX circuit is advantageous in that it contains both the internal and external integrated circuit chip interconnections. The inner leads are adjacent to and an integral part of the flexible circuitry pattern. Outer leads are not required because the individual inner leads are incorporated within the flexible circuitry pattern. In addition, the flexible circuitry pattern is supported by the flexible insulating substrate and electrically connected at the appropriate regions. Therefore outer lead bonds are not necessary and correspondingly the number of interconnections are substantially reduced. For these reasons, flexible circuitry technology has many advantages. FLEX circuitry significantly reduces the number of chip interconnections resulting in reduced lead inductance and lead-to-lead capacitance, as well as increased product reliability. In addition, the use of the FLEX circuitry permits smaller integrated circuits and interconnection patterns because the chip is mounted directly onto the patterned substrate.
Regardless of the method used for forming the electrical interconnection bond, for enhanced reliability it is desirable to control the amount of solderable surface area the bump on the integrated circuit contacts. If the solderable surface area, as defined by the conductor area and surrounding dielectric, is too large, the mass of solder which forms the bump has a propensity to sheer off during exposure to the widely varying temperature ranges. Therefore, the actual contact area between the individual solder bump on the integrated circuit and the contact region of the conductor must be optimally minimized.
Generally, the amount of contact area has been controlled and minimized by providing a conductor having a predetermined, optimal width in the contact region and by further providing a dielectric region, referred to as a solder dam, around the conductor in the contact area to prevent the solder from wicking down the conductor. The prior art has generally used a solder dam configuration which consists of a thick film of dielectric deposited over the conductor layer, wherein a trough is patterned within the dielectric layer so as to conform to the perimeter of the integrated circuit. Therefore, the trough forms a ring around the perimeter of the integrated circuit. Within the trough there is no dielectric material present. Lastly, the electrical contacts are formed between the conductors and integrated circuit within that trough region.
A significant disadvantage exists with respect to the prior art solder dam design. The alignment between the conductor layer and solder dam layer must be maintained quite strictly or substantial misalignment results between the two layers. When there is even slight misalignment between the layers, the conductors do not align with the solder dam or conductive bumps on the integrated circuit. Therefore, there may be electrical connections which are formed only partially or not at all, resulting in diminished integrity of the electrical connections and the electrical circuit as a whole.
It is therefore advantageous to provide an electrical interconnection lead comprising the conductor leads and a solder dam configuration, suitable for bonding to an integrated circuit for electrically interconnecting the integrated circuit to an electrical circuit on a substrate, which has both a high tolerance with respect to any misalignment between the components and also electrically efficient. It is further desirable that the interconnection lead have an improved solder dam configuration which permits the high tolerance for misalignment between the components. In addition, it is desirable that the provided interconnection lead be suitable for use with conventional thin and thick film technologies, tape automated bonding techniques or flexible circuitry techniques.